1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same. More particularly, the present invention relates to a semiconductor device comprising an interlayer insulating film with openings formed therein, and electrodes formed by filling the inside of the opening with a conductive substance.
2. Background Art
The width of an internal wiring pattern or the size of an interconnect opening are decreased as the density of integration of a semiconductor integrated circuit is increased. It has been attempted that a surface of an interlayer insulating film is leveled or smoothed to form a minute resist pattern by photolithography, and thereafter a metal plug is formed by filling a conductive substance into the inside of a minute interconnect opening.
In order to fill a conductive substance inside the interconnect opening formed in the interlayer insulating film, there has been a widely used method by which a conductive substance is formed over the entire surface of a wafer and is etched anisotropically. This manufacturing method will now be described with reference to FIGS. 15 through 19.
First, as shown in FIG. 15, on a semiconductor substrate 1, an isolation oxide film 2, gate electrodes 3, source/drain regions 4 for forming transistors, and a first interlayer insulating film 5 are formed in this sequence. Thus, the semiconductor wafer 100 is formed.
First interconnect openings 6 are formed in the first interlayer insulating film 5 until they reach the source/drain regions 4. The first interlayer insulating film 5 works to electrically insulates the gate electrodes 3 and to form a smooth surface on the wafer. More specifically, in order to accurately form a resist pattern by the photolithography at the time of formation of the first interconnect openings 6 or formation of a first wiring layer (which will be described later) on the first interlayer insulating film 5, it is significantly important to ensure a sufficient focal depth by smoothing the surface of the wafer through use of the first interlayer insulating film 5.
Next, as shown in FIG. 6, a conductor film (not shown) is formed over the entire internal surface of each of the first interconnect openings 6. A chemical vapor deposition technique is usually used for filling the inside of each minute-diameter interconnect opening 6 with a conductive substance without a void. In many cases, polycrystalline silicon, amorphous silicon, metal having a high melting point such as W, TiN or TiSi, or their compounds are used as material for a conductor film.
Subsequently, the conductor film is removed from the surface of the first interlayer insulating film 5 by subjecting the entire surface of the wafer to anisotropic etching. As a result, a first conductor plug 8 is formed in only the inside of each first interconnect opening 6. In consideration of the uniform thickness of the conductor film and the uniformity of the wafer surface after the etch-back, the wafer is usually etched to a depth which is equal to or greater than the thickness of the conductor film, thereby completely removing the conductor film on the surface of the first interlayer insulating film 5.
As shown in FIG. 16, if the wafer is insufficiently etched, etch residues 77 which are part of the conductor film are left on the surface of the wafer 100. If a first wiring layer (which will be described later) is formed over the surface of the wafer 100 in this state, electrical short circuits among wiring patterns may be caused. To prevent such failures, the wafer is usually etched to a depth which is greater than the thickness of the conductor film. As shown in FIG. 17, the wafer 100 is subjected to an etch-back treatment so as to completely eliminate etch residues from the surface of the wafer.
As mentioned previously, under the conventional method by which the conductor plug 8 is formed inside the interconnect opening 6 by anisotropically etching back the conductor film formed on the surface of the interlayer insulating film 5, the wafer is over-etched so as to prevent etch residues from being left on the surface of the wafer 100. For this reason, the surface of the first conductor plug 8 after over-etching is usually recessed about hundreds to thousands Angstroms below the surface of the first interlayer insulating film 5.
Next, as shown in FIG. 18, a second interlayer insulating film 9 is thinly formed on the wafer so as to cover the first interlayer insulating film 5 and the first conductor plug 8, and then a first wiring layer 10 is formed. The second interlayer insulating film 9 protects the surface of the conductor plug 8 when the first wiring layer 10 is formed by etching.
In recent years, with a view toward increasing the density of integration of a semiconductor integrated circuit device, an interval of the first wiring layers 10 is reduced, and the distance between the first wiring layer 10 and the first interconnect opening 6 are simultaneously reduced. If alignment errors arise during photolithography, the first wiring layer 10 may be formed so as to be partly superimposed on the first conductor plug 8. At that time, the second interlayer insulating film 9 prevents an electrical short circuit between the first wiring layer 10 and the first conductive plug 8.
If the surface of the first conductor plug 8 is recessed to a depth (D) of hundreds or more of Angstroms, a recess having substantially the same depth is formed on each conductor plug 8 even after formation of the second interlayer insulating film 9. Then, an etch residue 11 may remain in each recess after the first wiring layer 10 has been formed by etching.
Next, a third interlayer insulating film 12 is formed on the wafer, and the second interconnect openings 13 is formed through the third interlayer insulating film 12 to the surface of each first conductor plug 8. Then, the second interconnect openings 13 is filled with a second conductor plug 14. At this time, the etch residue 11 left in the first interconnect opening 6 may cause a failure such as an electrical short circuit between the first wiring layer 10 and the second conductor plug 14.
FIGS. 20 and 21 are illustrations for explaining the drawbacks in the conventional semiconductor integrated circuit. FIG. 20 is a plan view showing a first wiring layer 10 which is formed by the photolithography and through anisotropic etching. FIG. 21 is a cross-sectional view showing the cross-sectional structure of a wafer taken across line XXI--XXI shown in FIG. 20. These drawings corresponds to the manufacturing process shown in FIG. 18.
The first wiring layer 10 should be formed like a wiring pattern 10a. However, the first wiring layer such as wiring pattern 10b or 10c may be formed on the recess formed on the conductor plug 8, so that the etch residue 11 may be formed along the step of each recess. Although the etch residues 11 are insulated from the first conductor plugs 8 by the presence of the second interlayer insulating film 9, the etch residue 11 is in continuation with the first wiring layer 10.
Accordingly, as shown in FIG. 19, when the second conductor plugs 14 are formed, the first wiring layer 10 causes short circuits with the first conductor plug 8 and the second conductor plug 14 by way of the etch residue 11, thereby resulting in a failure.
In addition, as shown in FIGS. 16 through 19, a modified layer 55 is formed along the surface of the first interlayer insulating film 5 by means of fluorine-containing etching gas commonly used for etching back a conductor film 7. The modified layer causes the deterioration of electrical insulating characteristics of the interlayer insulating film 5. If a wiring layer is formed directly on the surface of the interlayer insulating film 5, a short-circuit failure may arise between the wiring patterns.
Further, when the second interlayer insulating film 9 is formed on the first interlayer insulating film 6 after etch-back, the second interlayer insulating film 9 may not be formed uniformly, resulting in the deterioration of uniform thickness of the wafer surface. The deterioration of uniform thickness of the wafer causes a deterioration of manufacturing yields of a semiconductor device or variations in the electrical characteristics of products.
In such a conventional technique, the conductor plugs 8 are formed by anisotropic etching, so that insufficient over-etching in etch-back process causes etch residues. On the other hand, excess over-ething results in an increase in the depth of the recess formed on the conductor plug 8, thereby causing a short-circuit failure between the wiring pattern and the conductor plug in the subsequent manufacture process.
FIG. 22 shows another conventional manufacturing method intended to solve drawbacks such as those mentioned previously. As shown in FIG. 22, in this conventional method, conductor plugs 8 in the interconnect openings 6 are formed by abrasion and elimination of only the conductor film on the interlayer insulating film 5 through use of a CMP (Chemical-and-Mechanical Polishing) method.
In a case where a conductive substance is abraded through use of an abrasive agent or a slurry for polishing a conductor, the surface of the interlayer insulating film 5 must be smoothed beforehand in a substantially complete manner through use of the CMP method using an abrasive agent for abrading an insulating film. The reason is that even when a wafer has a sufficient flatness to ensure a focal depth for photolithography, surface irregularities may be present in small degrees on the interlayer insulating film 5. Then, etch residues 77 will remain in depressions of steps when a conductor is abraded using an abrasive agent for a conductor.
This is caused because the interlayer insulating film (e.g., a silicon oxide film) 5 is not so much abraded as the conductor by the abrasive agent for a conductor. Etch residues remaining on the interlayer insulating film 5 cause short-circuit failures among wiring patterns in the subsequent manufacturing processes. Therefore, an interlayer insulating film must be smoothed by the CMP method before a plug is formed by abrading a conductor.
Referring to FIG. 23, an explanation will be given of problems associated with preliminary smoothing of the first interlayer insulating film 5 by the CMP method. In the case of a semiconductor memory device such as DRAM or SRAM, a gate electrode wiring pattern 3 is formed at a very high density in a memory array region which includes a plurality of memory elements. In contrast, a gate electrode wiring pattern is comparatively sparsely formed in a logic circuit region which controls the memory elements. For this reason, when the first interlayer insulating film 5 is smoothed by the CMP method, the interlayer insulating film is abraded at a higher rate in the logic circuit region, where the gate electrodes 3 are sparsely formed, than the interlayer insulating film in the memory array region. As a result, a level difference (H) arises in the surfaces of the first interlayer insulating films 5 after abrasion. When a first wiring layer is formed on the wafer by photolithography in a subsequent manufacturing process, defocusing arises to an extent corresponding to the level difference (H), thereby deteriorating the margin of error in the manufacturing process. Further, under the foregoing method, complicated manufacturing processes are required to abrade the interlayer insulating film 5, using the CMP method. Further, the interlayer insulating film 5 needs to be formed with additional thickness to be abraded, and thus the manufacturing cost is increased.
A method of simultaneously abrading a conductor film and an interlayer insulating film through use of an identical abrasive agent is described in Japanese Patent Application Laid-open No. 9-186237. Depending on the materials of the conductor film and the interlayer insulating film, a slight difference arises in polishing rate between the conductor film and the interlayer insulating film, which in turn causes residues of conductor film to be left on the surface of the wafer. In order to prevent such residues, it is necessary to sufficiently smooth the surface of the interlayer insulating film in some way beforehand. Consequently, in terms of reproducibility and manufacturing cost, the foregoing method presents problems. Further, the interlayer insulating film needs to be formed thick beforehand to allow abrasion by the CMP method. This requires deep interconnect openings to be formed anisotropically. Therefore, the dimensional control of the holes is difficult, and the manufacturing cost is increased.
The present invention has been contrived to solve the drawbacks in the conventional method of manufacturing a semiconductor device, and the object of the present invention is to provide a semiconductor device which prevents short circuits between wiring layers and conductor plugs.
Another object of the present invention is to provide a semiconductor device in which wiring patterns may be designed at much shorter distance and miniaturization of the semiconductor integrated circuit device is improved, as well as to provide a method of manufacturing such a semiconductor device.
To attain these objects, in a method of manufacturing a semiconductor device in the present invention, a conductor film is formed over the entire surface of a wafer after interconnect openings have been formed in an interlayer insulating film. Then, conductor plugs are formed inside the interconnect openings by anisotropic etching, and the interlayer insulating film is abraded by a CMP method to a depth of a recess of the conductor plug from the surface of the interlayer insulating film.